Obtaining adequate metal filling of via structures, when the thrust towards higher performance circuits demands thicker and demands thicker and thicker inter-metal dielectric coating with inevitably deeper vias, is approaching impossibility. The acceptance of poor metal step coverage into vias is no longer credible with customers, who demand better long term reliability.
Complex via-filling technologies, such as "blanket tungsten" or "self-aligned tungsten", are still in their infancy, with numerous problems in both the areas of equipment and process.
The use of conventional via formation techniques, with either sputtered or evaporated metalization, does not provide good via sidewall step coverage. CVD technology is promising, but is difficult to implement. The present invention is better, because it provides an improvement in metal step coverage, similar to that of CVD, but without introducing difficult process steps.
As is known, it is often desirable to smooth, or planarize, the top surface of a device at various stages in the fabrication of the semiconductor structure.
Commonly-owned U.S. Pat. No. 4,708,770 ("'770 patent"), entitled PLANARIZED PROCESS FOR FORMING VIAS IN SILICON WAFERS, issued Nov. 24, 1987 to Nicholas F. Pasch, discloses the use of dielectric pillars in selective areas of a device to enhance the planarization of said areas. More particularly, the patent is directed to the situation where a field oxide region is inherently higher than the adjacent diffusion region. A pillar is formed from a dielectric material overlying the diffusion area, such that the top surface of the dielectric material at the diffusion region is substantially at the same level as the top surface of the etched dielectric at the field oxide region. By this method, the distances or depths for etching vias (to an overlying metallization layer through a subsequent planarized dielectric layer) from the top surface of the structure to the metallization layer at the field oxide region and at the diffusion region are substantially the same (see column 1, lines 44-56). This is significant, because it allows vias to otherwise (without the pillar) deeper structures (metal over diffusion area) to be shallower, and shallower vias generally exhibit improved sidewall coverage of (overlying) metallization layer.
In the '770 patent, the possibility that the dielectric pillars could be used at all via locations on a given circuit, in order to enhance the step coverage of the subsequently formed via structure, is not disclosed. Rather, it is newly-disclosed in the present application.
It is noted, that in the abstract of the '770 patent, the pillar is located above the diffusion region "preferably", and that in the specification of the patent there is reference to vias at "one" location and "another" location (see column 3, lines 31-35), and that in claim 1 "first" and "second" via locations are referred to. However, the remaining disclosure of the '770 patent is specifically directed to the formation of pillars above the lower diffusion region to substantially equalize the height of subsequent metal above the pillar and above the field oxide region. Notably, as pointed out in claim 1 of the '770 patent, there is a layer of dielectric material (from which the pillar was formed) remaining over the field oxide and diffusion regions.
Commonly-owned U.S. Pat. No. 4,879,257 ("'257 Patent"), entitled PLANARIZATION PROCESS, issued to Roger Patrick on Nov. 7, 1989, discloses a method for forming a multilayer integrated circuit device wherein the resultant top surface thereof is substantially planar. As in the '770 patent, the problem being addressed in the '257 patent is problems in via formation resulting from the offset (increased) height of a field oxide region versus a diffusion region. Two solutions are proposed in the '257 patent. In a first embodiment, shown in FIGS. 1A-1E, a first level of metallization is deposited and etched to form runners 18 and 20. The runner 18 is above the diffusion region 16, and the runner 20 is above the higher field oxide region. A first, conformal layer 22 of dielectric is deposited over the runners. A second, conformal layer 24 of dielectric is then deposited over the first dielectric layer 22. Vias ("cavities") 26 are then formed for connecting a subsequent layer of metal 34 to the runners 18 and 20. Prior to the deposition of metal layer 34, the vias are (selectively) filled with metal plugs 28, and the entire structure is coated with a planar layer of photoresist 30. The photoresist 30, dielectric layer 24 and metal plugs 28 are then uniformly etched back, resulting in a planar surface 32 for subsequent deposition of a subsequent metal layer 34. In a second embodiment, shown in FIGS. 2A-2E, a blanket (non-selective), generally conformal layer of metal 36 is applied, which fills the vias 26 and overlays the second dielectric layer 24. A planar layer of photoresist 38 is then applied over the metal 36. The photoresist 38, second dielectric layer 24 and metal layer 36 are then uniformly etched back, resulting in a planar surface for subsequent deposition of a subsequent metal layer 34. In both embodiments, the resulting vias have different aspect ratios.
The '257 patent relies on chemical etching processes to achieve planarity, which necessitates 1) first depositing a planar, sacrificial layer (e.g., of photoresist), and 2) careful control over the chemistry with regard to the various materials sought to be uniformly etched back. In contrast thereto, in the present invention a chemical/mechanical process is used to polish back the conductor and dielectric layers to a completely planarized surface, and it is not necessary to begin with a planar (sacrificial) layer.